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ts 7003 page 1 ? 2012 touchstone semiconductor, inc. all rights reserved. features ? pin - compatible, single - channel high er - speed upgrade to max 1286 ? single - supply operation: +2.7v to +3.6v ? dnl & inl: 1lsb (max) ? 3 00ksps sampling rate ? low conversion - mode supply current: 0.95ma @ 3 00ksps ? low supply current in shutdown: 0.2a ? i nternal 10 - mhz track - and - hold ? internal 0.6%, 30ppm/oc +2.5v reference ? spi/qspi/microwire 3 - wire serial - interface ? 8 - pin , 3mm x 3mm tdfn - ep package applications process control and factory automation data and low - frequency signal acquisition portable data l ogging pen digitizers & tablet computers medical instrumentation battery - powered instruments description the ts7003 C a single - supply, single - channel, 12 - bit analog - to - digital converter (adc) - is touchstone semiconductors 1st successive - approximation ad c that combines a high - bandwidth track - and - hold (t/h), a high - speed serial digital interface, an internal +2.5v reference, and low conversion - mode power consumption. the ts7003 operates from a single +2.7v to+3.6v supply and dr aws less than 1ma at 300ksps. connecting directly to any spi?/qspi?/ microwire? microcontrollers and other interface - compatible computing devices, the ts7003s 3 - wire serial interface is easy to use and doesnt require separate, external logic. an external serial - interface clock cont rols the ts7003s conversion process and its output shift register operation. in pcb - space - conscious, low - power remote - sensor and data - acquisition applications, the ts7003 is an excellent choice for its low - power, ease - of - use, and small - package - footprint attributes. as a p in - compatible and higher - speed upgrade to the max1286, the ts7003 is fully specified over the - 40c to +85c temperature range and is available in a low - profile, 8 - pin 3x3mm tdfn package with an exposed back - side paddle. a 300ksps, single - supply, 12 - bit serial - o utput adc functional block dia gram t he touchstone semicondu c tor logo is a registered trademark of touchstone semiconductor, incorporated.
ts 7003 page 2 ts7003ds r1p0 rtfds absolu te maximum ratings v dd to gnd ................................ ................................ .. - 0.3v to +6v ain to gnd ................................ ..................... - 0.3v to (v dd + 0.3v) ref to gnd ................................ .................... - 0.3v to (v dd + 0.3v) digital inputs to gnd ................................ ................... - 0.3v to +6v dout to gnd ................................ ................. - 0.3v to (v dd + 0.3v) dout current ................................ ................................ ...... 25ma continuous power dissipation (t a = +70c) : 8 - pin tfdn33 - ep ( derate 12.5 mw/c above +70c) . 1000 mw operating temperature ranges : ts7003i ................................ ............................ - 40c to +85c storage temperature range ................................ . - 60c to +150c lead temperature ( s oldering, 10s) ................................ ..... +300c soldering temperature (r eflow) ................................ .......... +260c electrical and thermal s tresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifica tions is not implied. exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime . package/ordering inf ormation order number part marking carrier quantity ts 7003 itd 833 t p 7003i tape & reel ----- ts 7003 itd 833 t tape & reel 3000 lead - free program: touchstone semiconductor su pplies only lead - free packaging. consult touchstone semiconductor for products specified with wider operating temperature ranges.
ts7003 ts7003ds r1p0 page 3 rtfds electrical specifications v dd = +2.7v to +3.6v; f sclk = 4.8mhz, 50% duty cycle, 16 clocks/conversion cycle, 300ksps; 4.7f capacitor at ref; t a = - 40oc to +85oc , unless otherwise noted. typical values apply at t a = +25c. parameter symbol conditions min typ max units dc accuracy ( see note 1) resolution 12 bits relative accuracy inl see note 2 1.0 lsb differential nonlinearity dnl no missing codes over temperature 1.0 lsb offset error ze 6.0 lsb gain error ge see note 3 6.0 lsb gain - error temperature coefficient tcge 1.6 ppm/c dynamic specifications ( f in = 75khz sine wave, 2.5v pp , f sample = 300ksps, f sclk = 4.8mhz) signal - to - noise plus distortion ratio sinad 70 db total harmonic di stortion thd including the 5th harmonic - 80 db spurious - free dynamic range sfdr 80 db intermodulation distortion imd f a = 73khz, f b = 77khz 76 db full - power bandwidth fpbw - 3db point 10 mhz full - linear bandwidth flbw sinad > 68db 30 0 khz conversion rate conversion time t conv see note 4 3.3 s track/hold acquisition time t acq 625 ns aperture delay t ad 10 ns aperture jitter t aj < 50 ps serial clock frequency t sclk 0.5 4.8 mhz duty cycle 40 60 % analog input (ain) input voltage range v in 0 vref v input capacitanc e c in a 1 0 pf internal reference ref outp ut voltage v ref 2.48 5 2.50 2.5 15 v ref short - circuit current t a = +25c 15 ma ref output tempco tc vref 30 ppm/c load regulation see note 5; 0 to 0.75ma output load 3 5 mv/ma capacitive by pass at ref 4.7 10 f digital inputs (sclk, , ) input high voltage v inh 2. 4 v input low voltage v inl 0.8 v input hysteresis v hyst 0.2 v input leakage i in v inl = 0v or v inh = v dd 1 a input capacitance c ind 15 pf digital output (dout) output v oltage low v ol i sink = 5ma 0.4 v output voltage high v oh i source = 0.5ma v dd - 0.5 v three - state leakage current i l v cs = +3v 10 a three - state output capacitance c out v cs = +3v 15 pf power supply positive supply voltage v dd see note 6 2 .7 3.6 v positive supply current i dd see note 7; v dd = +3.6v 0.95 1.2 5 ma shutdown supply current i sh sclk = v dd , sh = gnd 0.2 2 a power - supply rejection psr v dd = +2.7v to 3.6v, midscale input 0.5 2. 5 mv
t s 7003 page 4 ts7003ds r1p0 rtfds timing specifications v dd = +2.7v to +3.6v, t a = - 40oc to +85oc, unless otherwise noted. parameter symbol conditions min typ max units sclk period t cp 208 ns sclk pulse - width high t ch 83 ns sclk pulse - width low t cl 83 ns cs fall to sclk rise setup t css 45 ns sclk rise to cs rise hold t csh 0 ns sclk rise to cs fall ignore t cso 45 ns cs rise to sclk rise ignore t cs1 45 ns sclk rise to dout hold t doh c load = 20pf 13 ns sclk rise to dout valid t dov c load = 20pf 100 ns cs rise to dout disable t dod c load = 20pf ; refer to figure 2 13 85 ns cs fall to dout enable t doe c load = 20pf ; refer to figure 1 85 ns cs pulse - width high t csw 100 ns note 1: tested at v dd = v dd(min) . note 2: relative accuracy is the deviation of the analog value a t any code from its theoretical value after the full - scale range has been calibrated. note 3: internal reference, offset, and reference errors nulled. note 4: conversion time is defined as the number of clock cycles multiplied by the clock period; clock ha s 50% duty cycle. note 5: external load should not change during conversion for specified accuracy. guaranteed specification limit of 2mv/ma because of production test limitations. note 6: electrical characteristics are guaranteed from v dd(min) to v dd(max) . for operations beyond this range, see typical operating characteristics. note 7: ts7003 tested with 20pf on dout and f sclk = 4.8mhz, 0 to 3v. dout = full scale.
ts 7003 ts7003ds r1p0 page 5 rtfds typical performance characteristics v dd = +3v; f sclk = 4.8mhz ; c load = 20pf; 4.7f capacitor at ref; t a = 25 oc , unless otherwise noted. integral nonlinearity inl - lsb digital output code - 0.4 - 0.3 - 0.2 - 0.1 0 0.1 1k 2k 0 3k offset error vs supply voltage power supply voltage - volt offset error - lsb - 0.2 - 0.8 - 1.4 - 1.8 2.7 3.06 3.24 3.42 2.88 temperature - o c - 15 35 60 85 10 - 0.5 - 1 - 2 - 1.5 1.2 0.8 0.6 - 0.2 0.2 differentia l nonlinearity dnl - lsb digital output code 4k 5k 1k 2k 0 3k 4k 5k 0.2 0.3 0.4 - 0.25 - 0.2 - 0.15 - 0.1 0 0.2 0.25 - 0.05 0.05 0.2 0.15 3.6 offset error - lsb o ffset error vs temperature - 40 1 0.5 0 0.6 0.4 0.2 - 0.2 0 gain error vs supply voltage power supply voltage - volt gain error - lsb gain error vs temperature temperature - o c - 15 35 60 85 10 gain error - lsb - 40 - 0.4 - 0.6 - 1 - 1.2 - 1.6 2.7 3.06 3.24 3.42 2.88 3.6 1.2 1 0.8 1 0.4 0 - 0.4
ts7003 page 6 ts7003ds r1p0 rtfds internal reference output vs supply voltage reference output - v power supply current vs power supply voltage power supply current vs temperature supply curent - m a 2.494 2.496 2.498 2.5 2.502 2.506 1 0.9 0.8 0.5 typical performance characteristics v dd = +3v; f sclk = 4.8mhz ; c load = 20pf; 4.7f capacitor at ref; t a = 25 oc , unless otherwise noted . power supply voltage - volt temperature - o c - 15 35 60 85 10 - 40 power supply voltage - volt 2.7 3.06 3.24 3.42 2.88 3.6 temperature - o c - 15 35 60 85 10 - 40 0.7 0.6 code = 1111 1111 1111 r load = c load = 10pf converting sclk = 4.8mhz static 1 0.9 0.8 0.5 0.7 0.6 supply curent - m a static, v dd = 3v converting, v dd = 3v 2.504 internal reference output vs temperature reference output - v 2.498 2.5 2.502 2.504 2.506 2.510 2.508 2.7 3.06 3.24 3.42 2.88 3.6
ts7003 ts7003ds r1p0 page 7 rtfds pin functions pin name function 1 vdd power supply voltage, +2.7v to +3.6v. 2 ain analog signal input; unipolar, 0 to vref input range. 3 sh sh the supply current to 0.2a (typ). analog and igital ground. connect the ts7003s g pin at one and only one point to the C quality 4.7f capacitor. cs cs gles state on sclks rising edge and is high impedance when cs figure 1 : output loading circuits for dout enable time (t doe ). figure 2 : output loading circuits for dout disable time (t do d ).
ts 7003 page 8 ts7003ds r1p0 rt f ds description of operation converter operation the ts7003 uses an input track - and - hold (t/h) and a successive - approximation register (sar) circuitry to convert an analog input signal to a digital 12 - bit output. no external - hold capacitor is needed for the track/hold circuit. figure 3 illustrates the ts 7003 in its simplest configuration. the ts7003 converts input signals within the 0v to v ref range in 3.3 s including the track - and - holds acquisition time. the serial interface requires only three digital lines (sclk, cs , and dout) and provides an easy i nterface to microprocessors (ps) and microcontrollers (cs). the ts7003 has two operating modes: normal and shutdown. toggling (or driving) the sh pin low shuts down the adcs and reduces supply current below 1 a when v dd 3.6v. open - circuiting or t oggling (or driving) the sh pin high or places the adcs into operational mode. toggling the cs pin to logic low initiates a conversion where the conversion result is available at dout in unipolar serial format. the serial data stream consists of thre e leading zeros followed by the data bits with the msb first. all transitions on the dout pin occur within 20ns after the low - to - high transition of sclk. serial interface timing details of the ts7003 are illustrated in figures 8 and 9. analog input fig ure 4 illustrates the sampling architecture of the analog - to - digital converters comparator. the full - scale input voltage is set by the ts7003s internal 2.5 - v reference. track - and - hold operation during track mode, the analog signal is acquired and store d on the internal hold capacitor. during hold mode, the track/hold switches sw1 and sw2 are opened thereby maintaining a constant input level to the converters sar subcircuit. during the acquisition phase with sw1 and sw2 on track, the input capacitor, c hold , is charged to the analog input (ain). toggling the cs pin low causes the acquisition process to stop. at this instant, track/hold switches sw1 and sw2 are moved to hold position and the input side of c hold is then switched to gnd. unbalancing node zero at the comparators input, the retained charge on c hold represents a sample of the input signal applied to the converter. in hold mode and to restore node zero to 0v within the limits of the converters 12 - bit resolution, the output of the capacitiv e digital - to - analog converter (the cdac) is adjusted during the remainder of the conversion cycle. in other words, the stored charge on c hold is transferred to the binary - weighted cdac where it is converted into a digital representation of the analog input signal. at end of the conversion figure 3 : ts7003 typical application circuit. figure 4: ts7003 equivalent input circuit details.
ts7003 ts7003ds r1p0 page 9 rtfds process, the input side of c hold is switched back to ain so as to be charged to the input signal again. an acs acquisition time is function of how fast its input capacitance can be charged. if an input signals driving - point source impedance is high, the acquisition time is lengthened and more time must be allowed between conversions. the acquisition time (t acq ) is the maximum time the adc requires to acquire the signal and is also the minimum time needed for the signal to be acquired. the ts7003s acquisition time is calculated from the following expression: t acq = 9 x (r s + r in ) x 10pf where r in = 100 (the ts7003s internal track/hold switch resistance), r s = the input signals source impedance, and t acq is never les s than 625 ns . because of the input structure of the ts7003 , sources with output impedances of 1k or less do not affect significantly the ac performance of the ts7003 . the ts7003 can still be used in applications where the source impedance is higher so lo ng as a 0.01f capacitor is connected between the analog input and g. limiting the acs input signal bandwidth, the use of an external, input capacitor forms an rc filter with the inputs source impedance. input bandwidth considerations since the ts70 03 s input track - and - hold circuit exhibits a 10 mhz small - signal bandwidth, it is possible to measure periodic signals and to digitize high - speed transient events with signal bandwidths higher than the ts7003 s sampling rate by using undersampling techniqu es. to avoid the aliasing of high - frequency signals into the frequency band of interest, the use of external anti - alias filter circuits (discrete or integrated) is recommended. the time constant of the external anti - alias filter should be set so as not to interfere with the desired signal bandwidth. analog input protection the ts7003 incorporates internal protection diodes that clamp the analog input between v dd and gnd. these internal protection diodes allow the ain pin to swing from gnd - 0.3v to v dd + 0.3v without causing damage to the ts7003 . however, for accurate conversions near full scale, the input signal must not exceed v dd by more than 50mv or be lower than gnd by 50mv. if the analog inputs can exceed 50mv beyond the supplies, then the current i n the forward - biased protection diodes should be limited to less than 2ma since large fault currents can affect conversion results. internal reference considerations the ts7003 has an internal voltage reference that is factory - trimmed to 2.5v. the inter nal reference output is connected to the ref pin and is also connected to the acs internal cac. the ref output can be used as a reference voltage source for other components external to the adc and can source up to 750a . to maintain conversion accuracy to within 1 lsb, a 4.7f capacitor from the ref pin to g is recommended. while larger - valued capacitors can be used to further reduce reference wide - band noise, larger capacitor values can increase the ts7003 s wake - up time when exiting from shutdown mode (see the using sh to reduce operating supply current section for more information). when in shutdown (that is, when sh = 0), the ts7003 s internal 2.5 - v reference is disabled. serial digital interface i nitialization after power - up and starting a conversion if the sh pin is not driven low upon an initial, cold - start condition, it may take up to 2 .5 ms for a fully - discharged 4.7f reference bypass capacitor to provide adequate charge for specified conversion accuracy. as a result, conversions should not be initiated during this reference capacitor charge - up delay. to initiate a conversion, the cs pin is toggled (or driven) low. at the cs s falling edge, the ts7003 s internal track - and - hold is placed in hold mode and a conversion is initiated. data can then be transferred out of the adc using an external serial clock.
ts 7003 page 10 ts7003ds r1p0 rt f ds figure 6: ts7003 shutdown operation. using the as to redu ce operating supply current power consumption can be reduced significantly by turning off the ts7003 in between conversions. figure 5 illustrates the ts7003 s average supply current versus conversion rate. the wake - up delay time (t wake ) is the time from when the sh pin is deasserted to the time when a conversion may be initiated (refer to figure 6). this delay time depends on how long the adc was in shutdown (refer to figure 7) because the external 4.7f reference bypass capacitor is discharged slowly when sh = 0 . timing and control details the cs and sclk digital inputs control the ts7003 s conversion - start and data - read operations. the acs serial - interface operations are illustrated in figures 8 and 9. a cs high - to - low transition initi ates the conversion sequence - the input track - and - hold samples the input signal level, the adc begins to convert, and the dout pin changes state from high impedance to logic low. the external sclk signal is used to drive the conversion process and is also used to transfer the converted data out of the adc as each bit of conversion is determined. the sclk signal transfers data after a low - to - high transition of the third (3 rd ) sclk pulse. after each subsequent sclk rising edge, transitions on the dout pin o ccur in 20ns. the third rising clock edge produces the msb of the conversion at dout, followed by the remaining bits. since there are twelve data bits and three leading zeros, at least fifteen rising clock edges are needed to transfer the entire data strea m. extra sclk pulses occurring after the conversion result has been completely transferred out and, before to a new, low - to - high transition on cs , produce a string trailing zeros at dout. in addition, the extra sclk pulses have no effect on converter ope ration. minimum conversion cycle time can be accomplished by: (a) toggling the cs pin high after reading the conversion results lsb; and (b), after the specified minimum time defined by t cs has elapsed, toggling the cs pin low again to initiate the n ext conversion. output data coding and transfer function conversion results at the ts7003 s out pin are straight binary data. figure 10 illustrates the nominal transfer function where code transitions occur halfway between successive integer lsb values . if v ref = +2.500v, then 1 lsb = 610v or 2.500v/4096. conversion rate - ksps supply curent - m a v dd = 3v dout = fs r l = c l = 10pf 100 10 1 0.1 0.1 1 100 1k 10 1k figure 5: ts7003 supply curre nt vs conversion rate
ts7003 ts7003ds r1p0 page 11 rtfds figure 8: ts7003 serial interface timing sequence figure 9: ts7003 serial interface timing specifications in detail. applications informa tion connection to indu stry - standard serial interfaces the ts7003 s serial interface is fully compatible with spi/qspi and microwire standard serial interfaces (refe r to figure 11). for serial interface operation with these standards, the cpus serial interface should be set to master mode so the cpu then generates the serial clock. second, the cpus serial clock should be configured to operate up to 4.8mhz. the proce ss to configure the serial clock and data transfer operation is as follows: 1) using a general - purpose i/o line from the cpu, the cs pin is driven low to start a conversion. dout transitions from high impedance to logic low. the sclk polarity should be low to start the conversion process correctly. 2) next, sclk is activated for a minimum of 15 sclk cycles where the first two sclks produce zeros at the dout pin. data at dout is formatted msb first and dout transitions occur 20ns after the third (3 rd ) sclk low - to - high transition. once the low - to - high sclk transition has occurred, data is valid at dout time in shutdown mode - sec reference power - up delay time - ms c ref = 4.7 f 2 1 0.5 0 0.1m 10m 1 10 100m 2.5 1.5 1m figure 7 : ts7003 reference power - up delay vs duration in shutdown mode
ts 7003 page 12 ts7003ds r1p0 rt f ds according to the t dov (sclk rise to dout valid) timing specification. valid output data can then be transferred into p or cs on sclk low - to - hig h transitions. 3) at or after the 15th sclk low - to - high transition, the cs pin can be toggled high to halt the transfer process. if the cs pin remains low and the sclk is still active, trailing zeros are transferred out after the lsb. 4) once the cs pin is held at logic high for at least t cs , a new conversion cycle is started when the cs pin is toggled low. if a conversion is aborted by toggling the cs pin high before the current conversion has completed, a new conversion cycle can only be starte d after a the adc has acquired the signal (t acq ). the cs pin must be held low and sclk active until all data bits are transferred out of the adc. as shown in figure 8, data can be transferred in two 8 - bit bytes or continuously. the bytes contain the res ult of the conversion padded with three leading 0s in the first 8 - bit byte and 1 trailing 0 in the second 8 - bit byte. spi and microwire interface details when using an spi or microwire interface, setting [cpol:cpha] = [0:0] configures the microcontrolle rs serial clock and sampling edge for the ts7003 . the conversion commences on a high - to - low transition of the cs pin. the dout pin transitions from a high - impedance state to a logic low, indicating a conversion is in progress. two consecutive 1 - byte dat a reads are required to transfer the full 12 - bit result from the adc. dout output data transitions occur on the sclks low - to - high transition and are transferred into the downstream microcontroller on the sclks low - to - high transition. the first byte cont ains three leading 0s and then five bits of the conversion result. the second byte contains the remaining seven bits of the conversion result and one trailing zero. refer to figure 11 for the circuit connections and to figure 12 for all timing details. qs pi details using a qspi microcontroller, setting [cpol:cpha] = [0:1] configures the microcontrollers serial clock and sampling edge for the ts7003 . unlike the spi, which requires two 1 - byte reads to transfer all 12 bits of data from the adc, the qspi a llows a minimum number of clock cycles necessary to transfer data from the adc to the microcontroller. thus, the ts7003 requires 15 sclk clock cycles from the microcontroller to transfer the 12 bits of data with no trailing zeros. as shown in figure 13, th e conversion results contain two leading 0s followed by the msb - first - formatted, 12 - bit data stream. figure 10 : adc unipolar transfer function for straight binary digital data. figure 11: ts7003 circuit connections to industry - standard serial interfaces.
ts7003 ts7003ds r1p0 page 13 rtfds figure 12: spi/microwire - ts7003 serial interface timing details with [cpol:cpha] = [0:0]. figure 13 : qspi - ts7003 serial interface timing details with [cpol:cpha] = [0:1]. pcb layout, ground plane manag ement, and capacitive bypassing for best performance, printed circuit boards should always be used and wire - wrap boa rds are not recommended. good pc board layout techniques ensure that digital and analog signal lines are kept separate from each other, analog and digital (especially clock) lines are not routed parallel to one another, and high - speed digital lines are not routed underneath the adc package. a recommended system ground connection is illustrated in figure 14. a single - point analog ground (star ground point) should be created at the acs gnd and separate from the logic ground. all analog grounds as well as t he acs g pin should be connected to the star ground. no other digital system ground should be connected to this ground. for lowest - noise operation, the ground return to the star grounds power supply should be low impedance and as short as possible. h igh - frequency noise on the v dd power supply may affect the acs high - speed comparator. therefore, it is necessary to bypass the v dd supply pin to the star ground with 0.1f and 1f capacitors in parallel and placed close to the acs pin 1. component lead lengths should be very short for optimal supply - noise rejection. if the power supply is very noisy, an optional 10 - resistor can b e used in conjunction with the bypass capacitors to form a low - pass filter as shown in figure 14. figure 14 : recommended power supply bypassing and star ground configuration.
ts7003 page 14 touchstone semiconductor, inc. ts7003ds r1p0 630 alder drive, milpitas, ca 95035 rt f ds +1 (408) 215 - 1220 ? www.touchstonesemi.com package outline draw ing 8 - pin 3mm x 3mm tdfn - ep package outline drawing (n.b., drawings are not to scale) information furnished by touchstone semiconductor is believed to be accurate and reliable. however, touchstone semiconductor does not assume any responsibility for its use nor for any infringements of patents or other rights of third parties that may result f rom its use , and all information provided by touchstone semiconductor and its suppliers is provided on an as is basis, without warranty of any kind . touchstone semiconductor reserves the right to change product specifications and product descriptions at any time without any advance notice. no license is granted by implication or oth erwise under any patent or patent rights of touchstone semiconductor. touchstone semiconductor assumes no liability for applications assistance or customer product design. customers are responsible for thei r products and applications using touchstone semic onductor components. to minimize the risk associated with customer products and applications, customers should provide adequate design and operating safeguards. trademarks and registered trademarks are the property of t heir respective owners. b o t t o m v i e w t o p v i e w 1 . 8 5 m a x 1 . 6 5 m i n 3 . 0 5 m a x 2 . 9 5 m i n 3 . 0 5 m a x 2 . 9 5 m i n p i n 1 m a r k i n g 0 . 2 0 r e f 0 . 2 5 r e f 0 . 3 5 r e f 1 . 6 0 m a x 1 . 4 0 m i n 0 . 5 m a x 0 . 3 m i n 0 . 3 5 m a x 0 . 2 5 m i n 0 . 6 5 r e f d e t a i l a 0 . 2 0 r e f 0 . 0 5 m a x 0 . 0 0 m i n d e t a i l a s i d e v i e w n o t e : c o n t r o l l i n g d i m e n t i o n s i n m i l i m e t e r s c o m p l i a n t w i t h j e d e c m o - 2 2 9 0 . 8 0 m a x 0 . 7 0 m i n 0 . 0 5 m a x 0 . 0 0 m i n 0 . 8 0 m a x 0 . 7 0 m i n 0 . 0 5 m a x 0 . 0 0 m i n

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